1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and more particularly to a semiconductor integrated circuit device having an error checking and correcting (ECC) circuit, and an error checking and correcting method thereof.
2. Description of the Related Art
With miniaturization, an increase in the capacity and a reduction in the power consumption of semiconductor memory devices, particularly, it becomes more difficult for a memory cell having a fine structure in the semiconductor memory device to attain a high reliability in the process and transistor characteristics. Since an SRAM among the semiconductor memories has memory cells each formed of a plurality of transistors (six transistors in a full CMOS type cell), it is difficult to form a cell with a small size and large capacity. On the other hand, since a memory cell of a DRAM is configured by one transistor and one capacitor, it is suitable for miniaturization and large capacity.
For example, it is considered that part of a memory system configured by use of SRAMs is replaced by a pseudo-SRAM (PSRAM) using DRAM cells to attain miniaturization in a small-sized portable electronic equipment by taking the feature of the DRAM into consideration. Generally, the row and column addresses are multiplexed in the DRAM and the addresses are not multiplexed in the SRAM. Therefore, if an interface for the SRAM is used as it is, the PSRAM is used without multiplexing the addresses. Further, since the DRAM requires the data refresh operation, it becomes necessary to incorporate an auto refresh circuit in an internal portion of the PSRAM.
Since the PSRAM utilizes DRAM cells, it is suitable for formation of a memory system of small size and large capacity. However, since it is necessary to periodically refresh data, the power consumption tends to become larger. Therefore, in the PSRAM, for example, an attempt is made to meet the requirement of power saving by setting the operation voltage as low as possible or setting the refresh cycle as long as possible.
However, as the power consumption is reduced more, it becomes more difficult to maintain the data holding characteristic of the DRAM cell, and it is therefore required to take a measure to prevent deterioration of the data holding characteristic. The deterioration of the data holding characteristic caused by power saving is not peculiar to the PSRAM and similarly occurs in a normal DRAM and a nonvolatile semiconductor device such as an EEPROM.
As a device which solves a problem of deterioration of the data holding characteristic, there is provided a semiconductor memory device having an error checking and correcting (ECC) circuit.
As a known reference of the semiconductor memory device having the ECC circuit, for example, documents 1, 2 exist.
Document 1: Jpn. Pat. Appln. KOKAI Publication No. 10-177800
Document 2: Jpn. Pat. Appln. KOKAI Publication No. 2003-59290
The semiconductor memory device having the ECC circuit can solve a problem of deterioration of the data holding characteristic caused by power saving. However, since a series of operations for ECC is additionally provided in addition to the normal read operation and write operation, the access speed is lowered.
Semiconductor memory devices, for example, PSRAMs which are frequently used in small-sized portable electronic equipments are required to attain a large power saving and enhance the access speed.